1. Field of the Invention
The present invention relates to a decoding circuit for decoding multibit digital data to output an electric signal (voltage) corresponding to the multibit digital data, and particularly relates to a decoding circuit used for digital to analog conversion by which multibit digital data is converted into an analog electric signal, and a display apparatus using such decoding circuit. Specifically, the present invention relates to a configuration of a decoding circuit of a digital/analog converter that generates pixel writing voltage in accordance with input pixel data in an image display apparatus.
2. Description of the Background Art
Where one candidate is to be selected from a plurality of output candidates, a decoding circuit is generally utilized. In the case of a digital signal of n bits, one candidate can be selected from 2^n output candidates, where the symbol “^” indicates a power. Thus, as compared with a configuration in which a selection signal is inputted to each output candidate, an occupancy area of the circuit can be reduced.
The configuration of the decoding circuit differs depending on application for which this decoding circuit is utilized. For example, where one of a plurality of signal lines is driven to a selected state as in an address decoding circuit in a memory circuit, a decoding circuit utilizing a logic gate such as a NAND type decoding circuit is used. According to combination (pattern) of bit values of n-bit digital data, a logic gate group drives one signal line out of the plurality of signal lines.
On the other hand, in the case where one electric signal is selected from a plurality of electric signals (indicating current or voltage) to be outputted, a ROM type decoding circuit using a switch matrix is generally used. A switching element in the switch matrix is selectively put into a conductive state in accordance with an input multibit digital signal, and a transmission path of one electric signal is decided. The one electric signal is transmitted to an output unit along this decided path. The connection between the switching element and the input multibit digital data is set uniquely and in a fixed manner, and a relation between an on/off states of the switching elements and the corresponding input multibit digital signal bits is also determined uniquely.
The ROM type decoding circuit as described above is in many cases utilized for a look-up table or the like, and one of specific applications of such decoding circuit is a digital/analog converting circuit that converts an input multibit digital data to an analog signal (voltage). Reference voltages corresponding to the respective levels which an input multibit digital data can represent are prepared. In a decoding operation, the reference voltage corresponding to a value of the inputted multibit digital data is selected. The values that input multibit digital data represents are discrete values, and the reference voltage levels are also discrete. This reference voltage takes a voltage level according to the bit value of an input digital data between a maximum value and a minimum value of the multibit digital data, and thus, a voltage resulting from converting the input multibit digital data to an analog voltage can be provided as an output voltage.
Such a digital/analog converting circuit is used in a driving circuit for generating a writing voltage to a pixel in a liquid crystal display apparatus. The reference voltage is selected corresponding to the input pixel data, and the selected reference voltage is written into a pixel electrode of a display element such as a liquid crystal element. In the case where the display element is the liquid crystal element, brightness of the pixel is set in accordance with the voltage between the pixel electrodes, an intermediate value between white and black can be represented in the liquid crystal element, and gradation display can be achieved. These liquid crystal elements are provided corresponding to red (R), green (G), and blue (B), respectively, thereby achieving the gradation display of a color image.
In the case where the data of pixels has n bits, the gradation displays of 2^n levels are enabled. Accordingly, for the reference voltage levels, 2^n levels are required. As an example, if n=6, then 2^6 is 64, and 64-level gradation display is enabled in each of red (R), green (G), and blue (B), so that multicolor display corresponding to 260,000 colors can be achieved. Moreover, if n=8, 256 (=2^8) level gradation display is enabled in each of red (R), green (G), and blue (B), so that multicolor display corresponding to 16,770,000 colors is enabled.
Now, a digital/analog converting circuit for one color is considered. In the case where the digital/analog converting circuit is implemented by the ROM type decoding circuit, in a configuration utilizing a switch matrix, simply, switching transistors receiving input digital signal bits respectively are connected in series corresponding to the respective reference voltage levels. In this case, (n×2^n) switching elements are required, which increases the decoding circuit in layout area. Here, “^” indicates a power. Accordingly, when a driving circuit is formed integrally with a display panel on the same chip, a chip area becomes large, which significantly hinders the downsizing of the display apparatus.
Configuration for reducing the size of the digital/analog converting circuit for generating pixel writing voltage in the pixel display apparatus are disclosed in Japanese Patent Laying-Open No. 2001-133754, Japanese Patent Laying-Open No. 2005-283777, and Japanese Patent Laying-Open No. 2003-241716.
In the configuration disclosed in Japanese Patent Laying-Open No. 2001-133754, a decoder is provided, in which based on a content of gradation selection bits introduced in a column direction, one of multilevel gradation voltage signals passes in a row direction and outputted. In each row, a least significant bit decoding unit and a higher-order bit decoding unit are provided. The least significant bit decoding unit selects and outputs one of the plurality of (two) gradation voltage signals in accordance with the least significant bit of the gradation selection bits. The higher-order bit decoding unit is provided corresponding to the least significant bit decoding unit, and selectively passes the gradation voltage signal in the corresponding row in accordance with the higher-order bits other than the least significant bit among the gradation selection bits. The higher-order bit decoding unit has a plurality of transistor elements arranged in series in each row, to which the different gradation selection bits are applied, respectively.
In this prior art reference, a signal line transmitting a gradation voltage signal is made common, and one of the plurality of gradation voltage signals selected by the lower-order bit is selected by the higher-order bit decoding unit and outputted. This reduces the number of the gradation voltage signal lines and the number of transistors arranged in a vertical direction in proportion with the number of gradations, to reduce the size in the vertical direction (direction in which the gradation voltages are arranged).
In Japanese Patent Laying-Open No. 2005-283777, a decoding circuit unit for selecting a gradation voltage is constructed by a dynamic circuit. In this decoding circuit, a transistor of the same logic is made common in decoders selecting adjacent gradation voltages. The gradation voltage is selected in accordance with a so-called “tournament method”, in which 2 to 1 selection is performed at each bit position. In this prior art reference, the decoder circuit is constructed by a dynamic circuit, and when display pixel data successively applied, gradation voltages are prevented from being simultaneously put into a selected state in gradation voltage selection based on such successive display pixel data.
In Japanese Patent Laying-Open No. 2003-241716, the number of arranged decoders is reduced by applying a time-divisionally driven gradation reference voltage. Specifically, first, the least significant bit is forced to an even-number value, and a gradation reference voltage at each even number position is selected and held at an output capacitance. Subsequently, gradation reference voltages in odd number positions are selectively selected in accordance with the input data bits. When the input data is an even number value, the gradation reference voltage in the odd number position is not selected, but the even number gradation voltage selected previously is outputted.
In the configuration of the decoding circuit disclosed in Japanese Patent Laying-Open No. 2001-133754, the transistor elements provided for the least significant bit are arranged in parallel in each row, and one of two gradation voltages is selected in each row in accordance with this least significant bit. In the higher-order bit decoding unit, a series body of the transistor elements selectively turning on in accordance with the higher-order bits is arranged in each row. Accordingly, this parallel arrangement increases a geometrical dimension in the horizontal direction (row extending direction), as compared with the configuration of a decoder in which a series body of the transistor elements turning on in accordance with the gradation voltage selection bits for each of the gradation voltages is arranged. Normally, in the image display apparatus, the decoding circuit selecting a gradation voltage is arranged corresponding to the data line of each pixel column. Accordingly, when the horizontal size of the decoding circuit increases, it becomes difficult to arrange the decoding circuit corresponding to each pixel column, which makes it difficult to achieve higher resolution of the display apparatus. In addition, in one decoding circuit, the higher-order bit decoding circuits arranged in the respective rows are commonly coupled to a gradation voltage Output line. Accordingly, the number of the transistor elements (switching elements) connected to this output line is reduced to only half times, as compared with the conventional configuration in which a series body of switching elements are arranged for each gradation reference voltage. As a result, there arises a problem in that parasitic capacitance associated with the output line is large, and a response speed of the decoding circuit slowed down, and thus, high-speed operation cannot be achieved.
Further in this prior art reference, the switching element selectively passing the gradation voltage is comprised of a single transistor element. Accordingly, for example, when the gradation voltage is an intermediate voltage, if a gate voltage is not set to a sufficient level, due to threshold voltage loss across this switching element, it is difficult to transmit the intermediate voltage precisely. Accordingly, in the configuration of the decoding circuit described in this prior art reference, there arises a problem in that it is difficult to set the output voltage within a specified time in a recent situation where the decoding time is reduced with an increase in number of pixels due to higher resolution, and others.
In the configuration described in Japanese Patent Laying-Open No. 2005-283777, the gradation voltage selection bits are decoded through the so-called “tournament method”, in which 2 to 1 selection is performed for each bit, and in accordance with the decoding result, a gradation voltage is selected to be transmitted to the output line. Accordingly, by sharing the decoding circuit unit, the transistor elements are reduced in number. However, the number of transistor stages of the decoder for the respective reference voltages is the same as in the case where the reference voltage is selected in accordance with a NAND type decoder configuration. Accordingly, it is difficult to reduce the vertical and horizontal sizes. In addition, transmission gates transmitting the respective gradation voltages are connected to the output line. Accordingly, the parasitic capacitance associated with this output line is large, which causes a problem that it is difficult to transmit a gradation voltage to the output line and stabilize the gradation voltage on the output line at high speed.
In the configuration disclosed in Japanese Patent Laying-Open No. 2003-241716, the gradation reference voltage is time-divisionally driven to be supplied, the number of the decoding circuits is reduced, and thus, the vertical size can be reduced. However, since the gradation reference voltage is transmitted through the time division, transition to a corresponding potential needs to be made within a predetermined time in each reference voltage line. Therefore, a higher-speed driving is required in the decoding circuit because of the time-division driving, and there arises a problem that it is difficult to generate sufficiently stabilized gradation voltage even in the situation where the decoding time is reduced due to the increase in number of pixels.
In addition, in the configuration of such prior art reference, the reference voltage lines are arranged in parallel to transistor rows constructing the decoding circuits, and are commonly provided for the decoding circuits arranged corresponding to the respective pixel data lines. Accordingly, there arises a problem that when this reference voltage lines are time divisionally driven, a potential fluctuation generates an analog noise through the capacitive coupling, which makes it difficult to generate the precise gradation voltage.
These configuration of the decoding circuits are not only limited to the application to the configuration of the digital/analog converting circuit that generates the analog voltage in accordance with input digital data, but, for example, in a configuration of a switch matrix circuit in which a transmission path of a certain signal is established by the decoding circuit, and the like, similar problems to those of these decoding circuits as described above arise.